From: kaf24@scramble.cl.cam.ac.uk Date: Thu, 1 Jul 2004 15:20:59 +0000 (+0000) Subject: bitkeeper revision 1.1041.1.8 (40e42bdbxRgFLnyaLAVXrbfK0RQrgg) X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~18074^2~12 X-Git-Url: https://dgit.raspbian.org/%22http:/www.example.com/cgi/%22https:/%22bookmarks://%22/%22http:/www.example.com/cgi/%22https:/%22bookmarks:/%22?a=commitdiff_plain;h=788b1c4771038b1d0bc1bdf1600f13cf584e98ea;p=xen.git bitkeeper revision 1.1041.1.8 (40e42bdbxRgFLnyaLAVXrbfK0RQrgg) Cleanups. --- diff --git a/.rootkeys b/.rootkeys index 92c6f42e9e..e843df9b04 100644 --- a/.rootkeys +++ b/.rootkeys @@ -281,7 +281,8 @@ 3ddb79bcBQF85CfLS4i1WGZ4oLLaCA xen/arch/x86/Rules.mk 3e5636e5FAYZ5_vQnmgwFJfSdmO5Mw xen/arch/x86/acpi.c 3ddb79bcsjinG9k1KcvbVBuas1R2dA xen/arch/x86/apic.c -3ddb79bcSC_LvnmFlX-T5iTgaR0SKg xen/arch/x86/boot/boot.S +3ddb79bcSC_LvnmFlX-T5iTgaR0SKg xen/arch/x86/boot/x86_32.S +40e42bdbNu4MjI750THP_8J1S-Sa0g xen/arch/x86/boot/x86_64.S 3ddb79bcUrk2EIaM5VsT6wUudH1kkg xen/arch/x86/delay.c 3e32af9aRnYGl4GMOaDKp7JdfhOGhg xen/arch/x86/domain_page.c 3ddb79bcecupHj56ZbTa3B0FxDowMg xen/arch/x86/entry.S diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index 7a6d659d0b..f6ef36afce 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -15,9 +15,9 @@ LOAD_BASE := 0x00100000 # Xen is loaded here # segment offsets from LINK_BASE-relative to LOAD_BASE-relative. # (NB. Linux gets round this by turning its image into raw binary, then # wrapping that with a low-memory bootstrapper.) -default: boot/boot.o $(OBJS) +default: boot/$(TARGET_SUBARCH).o $(OBJS) $(LD) -r -o arch.o $(OBJS) - $(LD) $(LDFLAGS) boot/boot.o $(ALL_OBJS) -o $(TARGET)-syms + $(LD) $(LDFLAGS) boot/$(TARGET_SUBARCH).o $(ALL_OBJS) -o $(TARGET)-syms objcopy -R .note -R .comment -S $(TARGET)-syms $(TARGET) $(BASEDIR)/tools/elf-reloc $(LINK_BASE) $(LOAD_BASE) $(TARGET) diff --git a/xen/arch/x86/boot/boot.S b/xen/arch/x86/boot/boot.S deleted file mode 100644 index 55a4cc4cc2..0000000000 --- a/xen/arch/x86/boot/boot.S +++ /dev/null @@ -1,249 +0,0 @@ -#include -#include -#include - -#define SECONDARY_CPU_FLAG 0xA5A5A5A5 - - .text - -ENTRY(start) - jmp hal_entry - - .align 4 - -/*** MULTIBOOT HEADER ****/ - /* Magic number indicating a Multiboot header. */ - .long 0x1BADB002 - /* Flags to bootloader (see Multiboot spec). */ - .long 0x00000002 - /* Checksum: must be the negated sum of the first two fields. */ - .long -0x1BADB004 - -hal_entry: - /* Set up a few descriptors: on entry only CS is guaranteed good. */ - lgdt %cs:nopaging_gdt_descr-__PAGE_OFFSET - mov $(__HYPERVISOR_DS),%ecx - mov %ecx,%ds - mov %ecx,%es - mov %ecx,%fs - mov %ecx,%gs - ljmp $(__HYPERVISOR_CS),$(1f)-__PAGE_OFFSET -1: lss stack_start-__PAGE_OFFSET,%esp - - /* Reset EFLAGS (subsumes CLI and CLD). */ - pushl $0 - popf - - /* CPU type checks. We need P6+. */ - mov $0x200000,%edx - pushfl - pop %ecx - and %edx,%ecx - jne bad_cpu # ID bit should be clear - pushl %edx - popfl - pushfl - pop %ecx - and %edx,%ecx - je bad_cpu # ID bit should be set - - /* Set up CR0. */ - mov %cr0,%ecx - and $0x00000011,%ecx # save ET and PE - or $0x00050022,%ecx # set AM, WP, NE and MP - mov %ecx,%cr0 - - /* Set up FPU. */ - fninit - - /* Set up CR4, except global flag which Intel requires should be */ - /* left until after paging is enabled (IA32 Manual Vol. 3, Sec. 2.5) */ - mov %cr4,%ecx - or mmu_cr4_features-__PAGE_OFFSET,%ecx - mov %ecx,mmu_cr4_features-__PAGE_OFFSET - and $0x7f,%ecx /* disable GLOBAL bit */ - mov %ecx,%cr4 - -#ifdef CONFIG_SMP - /* Is this a non-boot processor? */ - cmp $(SECONDARY_CPU_FLAG),%ebx - jne continue_boot_cpu - - call start_paging - lidt idt_descr - jmp start_secondary -#endif - -continue_boot_cpu: - add $__PAGE_OFFSET,%ebx - push %ebx /* Multiboot info struct */ - push %eax /* Multiboot magic value */ - - /* Initialize BSS (no nasty surprises!) */ - mov $__bss_start-__PAGE_OFFSET,%edi - mov $_end-__PAGE_OFFSET,%ecx - sub %edi,%ecx - xor %eax,%eax - rep stosb - - /* Copy all modules (dom0 + initrd if present) out of the Xen heap */ - mov (%esp),%eax - cmp $0x2BADB002,%eax - jne skip_dom0_copy - sub $__PAGE_OFFSET,%ebx /* turn back into a phys addr */ - mov 0x14(%ebx),%edi /* mbi->mods_count */ - dec %edi /* mbi->mods_count-- */ - jb skip_dom0_copy /* skip if no modules */ - mov 0x18(%ebx),%eax /* mbi->mods_addr */ - mov (%eax),%ebx /* %ebx = mod[0]->mod_start */ - shl $4,%edi - add %edi,%eax - mov 0x4(%eax),%eax /* %eax = mod[mod_count-1]->end */ - mov %eax,%ecx - sub %ebx,%ecx /* %ecx = byte len of all mods */ - mov $(DIRECTMAP_PHYS_END), %edi - add %ecx, %edi /* %edi = src + length */ - shr $2,%ecx /* %ecx = length/4 */ -1: sub $4,%eax /* %eax = src, %edi = dst */ - sub $4,%edi - mov (%eax),%ebx - mov %ebx,(%edi) - loop 1b -skip_dom0_copy: - - /* Initialize low and high mappings of all memory with 4MB pages */ - mov $idle_pg_table-__PAGE_OFFSET,%edi - mov $0x1e3,%eax /* PRESENT+RW+A+D+4MB+GLOBAL */ -1: mov %eax,__PAGE_OFFSET>>20(%edi) /* high mapping */ - stosl /* low mapping */ - add $(1<physical mapping table. Ring 0 can access all memory. */ -ENTRY(gdt_table) - .fill FIRST_RESERVED_GDT_ENTRY,8,0 - .quad 0x0000000000000000 /* unused */ - .quad 0x00cf9a000000ffff /* 0x0808 ring 0 4.00GB code at 0x0 */ - .quad 0x00cf92000000ffff /* 0x0810 ring 0 4.00GB data at 0x0 */ - .quad 0x00cfba000000c3ff /* 0x0819 ring 1 3.95GB code at 0x0 */ - .quad 0x00cfb2000000c3ff /* 0x0821 ring 1 3.95GB data at 0x0 */ - .quad 0x00cffa000000c3ff /* 0x082b ring 3 3.95GB code at 0x0 */ - .quad 0x00cff2000000c3ff /* 0x0833 ring 3 3.95GB data at 0x0 */ - .quad 0x0000000000000000 /* unused */ - .fill 2*NR_CPUS,8,0 /* space for TSS and LDT per CPU */ - - .org 0x1000 -ENTRY(idle_pg_table) # Initial page directory is 4kB - .org 0x2000 -ENTRY(cpu0_stack) # Initial stack is 8kB - .org 0x4000 -ENTRY(stext) -ENTRY(_stext) diff --git a/xen/arch/x86/boot/x86_32.S b/xen/arch/x86/boot/x86_32.S new file mode 100644 index 0000000000..ae1d72ad23 --- /dev/null +++ b/xen/arch/x86/boot/x86_32.S @@ -0,0 +1,193 @@ +#include +#include +#include + +#define SECONDARY_CPU_FLAG 0xA5A5A5A5 + + .text + +ENTRY(start) + jmp __start + + .align 4 + +/*** MULTIBOOT HEADER ****/ + /* Magic number indicating a Multiboot header. */ + .long 0x1BADB002 + /* Flags to bootloader (see Multiboot spec). */ + .long 0x00000002 + /* Checksum: must be the negated sum of the first two fields. */ + .long -0x1BADB004 + +bad_cpu: + jmp bad_cpu + +__start: + /* Set up a few descriptors: on entry only CS is guaranteed good. */ + lgdt %cs:nopaging_gdt_descr-__PAGE_OFFSET + mov $(__HYPERVISOR_DS),%ecx + mov %ecx,%ds + mov %ecx,%es + mov %ecx,%fs + mov %ecx,%gs + ljmp $(__HYPERVISOR_CS),$(1f)-__PAGE_OFFSET +1: lss stack_start-__PAGE_OFFSET,%esp + + /* Reset EFLAGS (subsumes CLI and CLD). */ + pushl $0 + popf + + /* CPU type checks. We need P6+. */ + mov $0x200000,%edx + pushfl + pop %ecx + and %edx,%ecx + jne bad_cpu # ID bit should be clear + pushl %edx + popfl + pushfl + pop %ecx + and %edx,%ecx + je bad_cpu # ID bit should be set + + /* Set up FPU. */ + fninit + + /* Set up CR4, except global flag which Intel requires should be */ + /* left until after paging is enabled (IA32 Manual Vol. 3, Sec. 2.5) */ + mov mmu_cr4_features-__PAGE_OFFSET,%ecx + and $0x7f,%cl # CR4.PGE (global enable) + mov %ecx,%cr4 + + cmp $(SECONDARY_CPU_FLAG),%ebx + je start_paging + + add $__PAGE_OFFSET,%ebx + push %ebx /* Multiboot info struct */ + push %eax /* Multiboot magic value */ + + /* Initialize BSS (no nasty surprises!) */ + mov $__bss_start-__PAGE_OFFSET,%edi + mov $_end-__PAGE_OFFSET,%ecx + sub %edi,%ecx + xor %eax,%eax + rep stosb + + /* Initialize low and high mappings of all memory with 4MB pages */ + mov $idle_pg_table-__PAGE_OFFSET,%edi + mov $0x1e3,%eax /* PRESENT+RW+A+D+4MB+GLOBAL */ +1: mov %eax,__PAGE_OFFSET>>20(%edi) /* high mapping */ + stosl /* low mapping */ + add $(1<physical mapping table. Ring 0 can access all memory. */ +ENTRY(gdt_table) + .fill FIRST_RESERVED_GDT_ENTRY,8,0 + .quad 0x0000000000000000 /* unused */ + .quad 0x00cf9a000000ffff /* 0x0808 ring 0 4.00GB code at 0x0 */ + .quad 0x00cf92000000ffff /* 0x0810 ring 0 4.00GB data at 0x0 */ + .quad 0x00cfba000000c3ff /* 0x0819 ring 1 3.95GB code at 0x0 */ + .quad 0x00cfb2000000c3ff /* 0x0821 ring 1 3.95GB data at 0x0 */ + .quad 0x00cffa000000c3ff /* 0x082b ring 3 3.95GB code at 0x0 */ + .quad 0x00cff2000000c3ff /* 0x0833 ring 3 3.95GB data at 0x0 */ + .quad 0x0000000000000000 /* unused */ + .fill 2*NR_CPUS,8,0 /* space for TSS and LDT per CPU */ + + .org 0x1000 +ENTRY(idle_pg_table) # Initial page directory is 4kB + .org 0x2000 +ENTRY(cpu0_stack) # Initial stack is 8kB + .org 0x4000 +ENTRY(stext) +ENTRY(_stext) diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S new file mode 100644 index 0000000000..b489734ded --- /dev/null +++ b/xen/arch/x86/boot/x86_64.S @@ -0,0 +1,185 @@ +#include +#include +#include + +#define SECONDARY_CPU_FLAG 0xA5A5A5A5 + + .text + .code32 + +ENTRY(start) + jmp __start + + .align 4 + +/*** MULTIBOOT HEADER ****/ + /* Magic number indicating a Multiboot header. */ + .long 0x1BADB002 + /* Flags to bootloader (see Multiboot spec). */ + .long 0x00000002 + /* Checksum: must be the negated sum of the first two fields. */ + .long -0x1BADB004 + +bad_cpu: + jmp bad_cpu + +__start: + /* We begin by interrogating the CPU for the presence of long mode. */ + mov $0x80000000,%eax + cpuid + cmp $0x80000000,%eax # any function > 0x80000000? + jbe bad_cpu + mov $0x80000001,%eax + cpuid + bt $29,%edx # Long mode feature? + jnc bad_cpu + + /* Set up a few descriptors: on entry only CS is guaranteed good. */ + lgdt %cs:nopaging_gdt_descr-__PAGE_OFFSET + mov $(__HYPERVISOR_DS),%ecx + mov %ecx,%ds + mov %ecx,%es + mov %ecx,%fs + mov %ecx,%gs + ljmp $(__HYPERVISOR_CS32),$(1f)-__PAGE_OFFSET +1: lss stack_start-__PAGE_OFFSET,%esp + + /* Reset EFLAGS (subsumes CLI and CLD). */ + pushl $0 + popf + + /* Set up FPU. */ + fninit + + /* Set up CR4, except global flag which Intel requires should be */ + /* left until after paging is enabled (IA32 Manual Vol. 3, Sec. 2.5) */ + mov mmu_cr4_features-__PAGE_OFFSET,%ecx + and $0x7f,%cl # CR4.PGE (global enable) + mov %ecx,%cr4 + + cmp $(SECONDARY_CPU_FLAG),%ebx + je start_paging + + add $__PAGE_OFFSET,%ebx + push %ebx /* Multiboot info struct */ + push %eax /* Multiboot magic value */ + + /* Initialize BSS (no nasty surprises!) */ + mov $__bss_start-__PAGE_OFFSET,%edi + mov $_end-__PAGE_OFFSET,%ecx + sub %edi,%ecx + xor %eax,%eax + rep stosb + + /* Initialize low and high mappings of all memory with 4MB pages */ + mov $idle_pg_table-__PAGE_OFFSET,%edi + mov $0x1e3,%eax /* PRESENT+RW+A+D+4MB+GLOBAL */ +1: mov %eax,__PAGE_OFFSET>>20(%edi) /* high mapping */ + stosl /* low mapping */ + add $(1<mods_count-1].mod_end - mod[0].mod_start); + if ( initial_images_end > (max_page << PAGE_SHIFT) ) + { + printk("Not enough memory to stash the DOM0 kernel image.\n"); + for ( ; ; ) ; + } + memmove((void *)initial_images_start, /* use low mapping */ + (void *)mod[0].mod_start, /* use low mapping */ + mod[mbi->mods_count-1].mod_end - mod[0].mod_start); + if ( opt_xenheap_megabytes > XENHEAP_DEFAULT_MB ) { printk("Xen heap size is limited to %dMB - you specified %dMB.\n", @@ -214,10 +226,6 @@ void cmain(unsigned long magic, multiboot_info_t *mbi) init_frametable((void *)FRAMETABLE_VIRT_START, max_page); - /* Initial images stashed away above DIRECTMAP area in boot.S. */ - initial_images_start = DIRECTMAP_PHYS_END; - initial_images_end = initial_images_start + - (mod[mbi->mods_count-1].mod_end - mod[0].mod_start); #elif defined(__x86_64__) diff --git a/xen/include/asm-x86/config.h b/xen/include/asm-x86/config.h index af0172df90..f61f6aeedd 100644 --- a/xen/include/asm-x86/config.h +++ b/xen/include/asm-x86/config.h @@ -164,7 +164,8 @@ extern void __out_of_line_bug(int line) __attribute__((noreturn)); #define DIRECTMAP_PHYS_END (40*1024*1024) /* Hypervisor owns top 64MB of virtual address space. */ -#define HYPERVISOR_VIRT_START (0xFC000000UL) +#define __HYPERVISOR_VIRT_START 0xFC000000 +#define HYPERVISOR_VIRT_START (0xFC000000UL) /* * First 4MB are mapped read-only for all. It's for the machine->physical